The flexibility of field programmable gate arrays (FPGAs) makes them ideal for all kinds of applications from smartNICs, telecom networks, and even for emulating retro game consoles.
However, AMD’s – formerly Xilinx’s – latest Versal FPGAs unveiled Tuesday can do a little better than mimic a 30-year-old microprocessor. The components are designed to emulate, test, and debug chips before they are even built.
Chip taping for manufacturing is a very expensive prospect, and even more so if you discover a defect after the fact. Using these FPGAs, chip designers can “create a digital twin or a digital version of their upcoming ASIC or SOC earlier than the silicon tape out,” said Rob Bauer, senior product line manager for AMD’s Versal family. The register. “They can verify, they can start developing the software earlier in the design cycle, etc.”
According to Bauer, this will only become more difficult for chipmakers as the transition to advanced packaging techniques such as 2.5D and 3D chiplet architectures. “If you’re a chip designer, you’re no longer doing verification and software development for a single die, you’re doing it for a multi-die chiplet-based device,” he explained.
This is where AMD is positioning its Versal Premium VP1902. Measuring approximately 77x77mm, the massive chip boasts 18.5 million logic cells – twice that of the outgoing VU19P – as well as dedicated Arm cores for control-plane operations, and onboard networking to help -debug.
The idea here is that by integrating general compute and networking functions, less of the FPGA logic is used by the I/O, debugging or control plane, and more of it for emulating the ASIC or SoC.
In addition to doubling the gate density, AMD says the part also offers twice the bandwidth, which translates to a higher effective cloud rate when emulating silicon. Meanwhile, the chip features a new chiplet architecture that places four FPGA tiles in quadrants, which Bauer says helps to reduce latency and congestion as data moves between chips.
While this may all sound impressive, anyone who has spent any time playing with emulation will know that it tends to be very inefficient, slow, and expensive compared to running on native hardware, and the situation is no different here.
Emulating modern SoCs with billions of transistors is a fairly resource intensive process to begin with. Depending on the size and complexity of the chip, Bauer says dozens or even hundreds of FPGAs spanning multiple racks may be needed, and even then the clock speeds are severely limited compared to what can be seen. you on hard silicon.
According to AMD, while only 24 devices are required to emulate a billion logic gates, it can be scaled out to support up to 60 billion gates at clock speeds in excess of 50MHz.
Bauer says the effective clock rate depends on the number of FPGAs involved. “For example, if you have a piece of IP that can live on a single VP1902, you will see higher performance,” he said.
While AMD’s latest FPGA is aimed more at chip makers, the company says the chips are also suitable for companies doing firmware and test, IP block and subsystem prototyping, peripheral validation, and other cases of test use.
For compatibility, we’re told the new chip will take advantage of the same underlying Vivado ML software development suite as the company’s previous FPGAs. AMD says it is also working in partnership with leading EDA vendors, such as Cadence, Siemens and Synopsys, to add support for more advanced chip features.
AMD’s VP1902 is scheduled to begin sampling to customers in Q3 with general availability beginning in early 2024. ®
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